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MC74AC377, MC74ACT377 Octal D Flip-Flop with Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
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PDIP-20 N SUFFIX CASE 738
20 1
* * * * * * * * * * *
Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ACT377 Has TTL Compatible Inputs MSL = 1 for all Surface Mount Chip Complexity: 292 FETS or 73 Gates
20 1
SO-20 DW SUFFIX CASE 751
20 1
TSSOP-20 DT SUFFIX CASE 948E
20 1
EIAJ-20 M SUFFIX CASE 967
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2001
1
May, 2001 - Rev.6
Publication Order Number: MC74AC377/D
MC74AC377, MC74ACT377
VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 D0 D1 D2 D3 D4 D5 D6 D7 CP CE O0 O1 O2 O3 O4 O5 O6 O7 1 CE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND
Figure 2. LOGIC SYMBOL
Figure 1. Pinout: 20-Lead Packages Conductors (Top View)
PIN NAMES
PIN D0-D7 CE Q0-Q7 CP FUNCTION
MODE SELECT-FUNCTION TABLE
Inputs Operating Mode Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input Load 1 Load 0 Hold (Do Nothing) X CP CE L L H H Dn H L X X Qn H L No Change No Change Outputs
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition
D0 CE
D1
D2
D3
D4
D5
D6
D7
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
CP O0 O1 O2 O3 O4 O5 O6 O7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 3. LOGIC DIAGRAM
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MC74AC377, MC74ACT377
MAXIMUM RATINGS*
Symbol VCC Vin Vout Iin Iout ICC Tstg JA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Thermal Resistance (Junction to Ambient) SOIC, DW TSSOP, DT PDIP, N Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) VCC = 5.5 V; TA = 125C (Note 4) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 -65 to +150 97 129 69 > 2000 > 200 > 1000 > 100 Unit V V V mA mA mA C C/W
VESD
ESD Withstand Voltage
V
ILatch-Up
Latch-Up Performance
mA
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Ri and Fall Time (Note 5) I t Rise d F ll Ti (N t AC Devices except Schmitt Inputs AC exce t In uts VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH In ut Input Rise and Fall Time (Note 6) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current -- High -40 25 VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 150 40 25 10 8.0 140 85 -24 ns/V C C mA mA ns/V Typ 5.0 5.0 Max 6.0 5.5 VCC V V Unit
IOL Output Current -- Low 24 5. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 6. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74AC377, MC74ACT377
74AC - DC CHARACTERISTICS
TA = +25C +25 C Symbol VIH Parameter Minimum High Level Input Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD Maximum Input Leakage Current Maximum Input Leakage Current 5.5 5.5 5.5 0.002 0.001 0.001 Typ 1.50 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 TA = -40C to +85C Unit V V V V V V V V V V V V V V V V V V A mA mA Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A
Guaranteed Limits 2.10 3.15 3.85 0.90 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 2.10 3.15 3.85 0.90 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75
VIL
Maximum Low Level Input Voltage
VOH
Minimum High Level Output Voltage
*VIN = VIL or VIH IOH IOUT = 50 A
-12 mA -24 mA -24 mA
*VIN = VIL or VIH IOH VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min
-12 mA -24 mA -24 mA
ICC Maximum Quiescent Supply Current 5.5 8.0 80 A VIN = VCC or GND *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
74AC - AC CHARACTERISTICS For Figures and Waveforms, See Figures 4, 5, and 6.
TA = +25C +25 C CL = 50 pF Typ TA = -40C to +85C 40 C +85 C CL = 50 pF Max Min 75 125 13.0 9.0 13.0 10.0 1.5 1.5 2.0 1.5 14.0 10.0 14.5 11.0 Max Unit MHz ns ns
Symbol fmax tPLH tPHL
Parameter Maximum Clock Frequency Propagation Delay Propagation Delay CP to Qn CP to Qn
VCC* (V) 3.3 5.0 3.3 5.0 3.3 5.0
Min 90 140 3.0 2.0 3.5 2.5
* Voltage Range 3.3 V is 3.3 V 0.3 V; Voltage Range 5.0 V is 5.0 V 0.5 V.
74AC - AC OPERATING REQUIREMENTS
TA = +25C +25 C CL = 50 pF Symbol ts th ts th tw Parameter Setup Time, HIGH or LOW Hold Time, HIGH or LOW Setup Time, HIGH or LOW Hold Time, HIGH or LOW CP Pulse Width Dn to CP Dn to CP CE to CP CE to CP HIGH or LOW VCC* (V) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Typ TA = -40C to +85C 40 C +85 C Guaranteed Minimum 5.5 4.0 0 1.0 6.0 4.0 0 1.0 5.5 4.0 6.0 4.5 0 1.0 7.5 4.5 0 1.0 6.0 4.5 Unit ns ns ns ns
ns
* Voltage Range 3.3 V is 3.3 V 0.3 V; Voltage Range 5.0 V is 5.0 V 0.5 V.
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MC74AC377, MC74ACT377
74ACT - DC CHARACTERISTICS
TA = +255C Symbol VIH Parameter Minimum High Level Input Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD Maximum Input Leakage Current Additional Max. ICC/Input Minimum Dynamic Output Current 5.5 5.5 5.5 0.6 0.001 0.001 Typ 1.5 1.5 1.5 1.5 4.49 5.49 TA = -405C to +855C Unit V Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 A *VIN = VIL or VIH IOH IOUT = 50 A *VIN = VIL or VIH IOH VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND -24 mA -24 mA -24 mA -24 mA
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 80
VIL
Maximum Low Level Input Voltage
V
VOH
Minimum High Level Output Voltage
V V V V A mA mA A
ICC Maximum Quiescent Supply Current 5.5 8.0 *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
74ACT - AC CHARACTERISTICS For Figures and Waveforms -- See Figures 4, 5, and 6.
TA = +25C +25 C CL = 50 pF Symbol fmax tPLH Parameter Maximum Clock Frequency Propagation Delay CP to Qn CP to Qn VCC* (V) 5.0 5.0 5.0 Min 140 3.0 3.5 9.0 10 Typ Max TA = -40C to +85C 40 C +85 C CL = 50 pF Min 125 2.5 2.5 10 11 Max Unit MHz ns ns
tPHL Propagation Delay *Voltage Range 5.0 V is 5.0 V 0.5 V.
74ACT - AC OPERATING REQUIREMENTS
TA = +25C +25 C CL = 50 pF Symbol ts th ts th Parameter Setup Time, HIGH or LOW Hold Time, HIGH or LOW Setup Time, HIGH or LOW Hold Time, HIGH or LOW Dn to CP Dn to CP CE to CP CE to CP HIGH or LOW VCC* (V) 5.0 5.0 5.0 5.0 5.0 Typ TA = -40C to +85C -40 C +85 C CL = 50 pF Guaranteed Minimum 4.5 1.0 4.5 1.0 4.0 5.5 1.0 5.5 1.0 4.5 Unit ns ns ns ns ns
tw CP Pulse Width *Voltage Range 5.0 V is 5.0 V 0.5 V.
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MC74AC377, MC74ACT377
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 90 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
SWITCHING WAVEFORMS
tr CLOCK 50% tw 1/fmax tPLH Q 50% tPHL CLOCK GND tf VCC CE 50% tsu th VCC 50% GND VCC
Figure 4.
Figure 5.
VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND
Figure 6.
450 W OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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MC74AC377, MC74ACT377
ORDERING INFORMATION
Device MC74AC377N MC74ACT377N MC74AC377DW MC74AC377DWR2 MC74ACT377DW MC74ACT377DWR2 MC74AC377DT MC74AC377DTR2 MC74ACT377DT MC74ACT377DTR2 MC74AC377M MC74AC377MEL MC74ACT377M MC74ACT377MEL Package PDIP-20 PDIP-20 SOIC-20 SOIC-20 SOIC-20 SOIC-20 TSSOP-20 TSSOP-20 TSSOP-20 TSSOP-20 EIAJ-20 EIAJ-20 EIAJ-20 EIAJ-20 Shipping 18 Units/Rail 18 Units/Rail 38 Units/Rail 1000 Tape & Reel 38 Units/Rail 1000 Tape & Reel 75 Units/Rail 2500 Tape & Reel 75 Units/Rail 2500 Tape & Reel 40 Units/Rail 2000 Tape & Reel 40 Units/Rail 2000 Tape & Reel
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MC74AC377, MC74ACT377
MARKING DIAGRAMS
PDIP-20 MC74AC377N AWLYYWW SO-20 AC377 AWLYYWW TSSOP-20 EIAJ-20
AC 377 ALYW
74AC377 AWLYWW
MC74ACT377N AWLYYWW
ACT377 AWLYYWW
ACT 377 ALYW
74ACT377 AWLYWW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
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MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX 20 PIN PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
SO-20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74AC377, MC74ACT377
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
EIAJ-20 M SUFFIX 20 PIN PLASTIC EIAJ PACKAGE CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
b 0.13 (0.005)
M
A1 0.10 (0.004)
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E c
20
11
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC74AC377, MC74ACT377
Notes
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MC74AC377, MC74ACT377
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MC74AC377/D

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